Cypress Semiconductor /psoc63 /SCB0 /I2C_CTRL

Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 SCB clock periods constitute the high phase of a bit period. The valid range is [5, 15] with input signal median filtering and [4, 15] without input signal median filtering.

The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the SCB clock wrt. the regular interface (IF) high time to guarantee functional correct behavior. With input signal median filtering, the IF high time should be >= 6 SCB clock cycles and <= 16 SCB clock cycles. Without input signal median filtering, the IF high time should be >= 5 SCB clock cycles and <= 16 SCB clock cycles.

Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 SCB clock periods constitute the low phase of a bit period. The valid range is [7, 15] with input signal median filtering and [6, 15] without input signal median filtering.

The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the SCB clock wrt. the regular (no stretching) interface (IF) low time to guarantee functionally correct behavior. With input signal median filtering, the IF low time should be >= 8 SCB clock cycles and <= 16 IP clock cycles. Without input signal median filtering, the IF low time should be >= 7 SCB clock cycles and <= 16 SCB clock cycles.

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This field is used during an address match or general call address in internally clocked mode Only used when:

• EC_AM_MODE is ‘0’, EC_OP_MODE is ‘0’, S_GENERAL_IGNORE is '0] and non EZ mode. Functionality is as follows:
• 1: a received (matching) slave address is immediately NACK’d when the receiver FIFO is full.
• 0: clock stretching is performed (till the receiver FIFO is no longer full).

For externally clocked logic (EC_AM is ‘1’) on an address match or general call address (and S_GENERAL_IGNORE is ‘0’). Only used when (NOT used when EC_AM is ‘1’ and EC_OP is ‘1’ and address match and EZ mode):

• EC_AM is ‘1’ and EC_OP is ‘0’.
• EC_AM is ‘1’ and general call address match.
• EC_AM is ‘1’ and non EZ mode. Functionality is as follows:
• 1: a received (matching or general) slave address is always immediately NACK’d. There are two possibilities: 1). the SCB clock is available (in Active system power mode) and it handles the rest of the current transfer. In this case the I2C master will not observe the NACK. 2).SCB clock is not present (in DeepSleep system power mode). In this case the I2C master will observe the NACK and may retry the transfer in the future (which gives the internally clocked logic the time to wake up from DeepSleep system power mode).
• 0: clock stretching is performed (till the SCB clock is available). The logic will handle the ongoing transfer as soon as the clock is enabled.

Only used when:

• non EZ mode Functionality is as follows:
• 1: a received data element byte the slave is immediately NACK’d when the receiver FIFO is full.
• 0: clock stretching is performed (till the receiver FIFO is no longer full).

Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When ‘0’, no loopback When ‘1’, loopback is enabled internally in the peripheral, and as a result unaffected by other I2C devices. This allows a SCB I2C peripheral to address itself.

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